1. Field of the Invention
The present invention relates generally to vertical transistors and more specifically to a method of reducing the current gain or Beta of vertical transistors.
2. Description of the Prior Art
Because of the relatively simple implementation, the vertical transistor is a common device structure where the substrate plays an active part in the isolation structure, for instance, junction isolation. The transistor current gain is dependent upon resistivity of the epitaxial base layer and its thickness. The thickness is tightly controlled sinced the base width can be as great as 10 times greater than in the typical double diffused transistor. These vertical transistors are effective devices because the epitaxial base region achieves good lifetimes for carriers and a large collector-base junction enable carriers injected into the base to be collected by the substrate collector.
One method for reducing the beta transistor is illustrated in U.S. Pat. No. 3,770,519 wherein an emitter region is diffused into a high concentration impurity region of opposite conductivity type. This approach reduces the efficiency of the emitter.
There exists a need for a method of fabricating simultaneously a plurality of vertical transistors having individually selected current gains.